The present invention relates to the field of manufacturing semiconductor devices and, more particularly, to an improved semiconductor device comprising silicon on insulator (SOI) and bulk silicon technology.
An important aim of ongoing research in the semiconductor industry is increasing semiconductor performance while decreasing power consumption in semiconductor devices. Planar transistors, such as metal oxide semiconductor field effect transistors (MOSFET) are particularly well suited for use in high-density integrated circuits. As the size of MOSFET and other devices decrease, the dimensions of source/drain regions channel regions, and gate electrodes of the devices, also decrease.
The design of ever-smaller planar transistors with short channel lengths makes it necessary to provide very shallow source/drain junctions. Shallow junctions are necessary to avoid lateral diffusion of implanted dopants into the channel, since such diffusion disadvantageously contributes to leakage currents and poor breakdown performance. Shallow source/drain junctions, on the order of 1,000 xc3x85 or less thick, are generally required for acceptable performance in short channel devices.
Silicon on insulator (SOI) technology allows the formation of high-speed, shallow-junction devices. In addition, SOI devices improve performance by reducing parasitic junction capacitance. Although, SOI technology improves the performance of shallow-junction devices, devices that require deeper junctions do not benefit from SOI. For example, devices which are temperature sensitive or which require a deep implant perform better when formed in the bulk substrate.
Strained silicon technology also allows the formation of higher speed devices. Strained-silicon transistors are created by depositing a graded layer silicon germanium (SiGe) on a bulk silicon wafer. A thin layer of silicon is subsequently deposited on the SiGe. The distance between atoms in the SiGe crystal lattice is greater than the distance between atoms in an ordinary silicon crystal lattice. Because there is a natural tendency of atoms inside different crystals to align with one another when one crystal is formed on another crystal, when silicon is deposited on top of SiGe the silicon atoms tend to stretch or xe2x80x9cstrainxe2x80x9d to align with the atoms in the SiGe lattice. Electrons in the strained silicon experience less resistance and flow up to 80% faster than in ordinary crystalline silicon.
Shallow trench isolation (STI) provides another technique to shrink device size. The use of STI significantly shrinks the area needed to isolate transistors better than local oxidation of silicon (LOCOS). STI also provides superior latch-up immunity, smaller channel width encroachment, and better planarity. The use of STI techniques eliminates the bird""s-beak frequently encountered with LOCOS.
The term semiconductor devices, as used herein, is not to be limited to the specifically disclosed embodiments. Semiconductor devices, as used herein, include a wide variety of electronic devices including flip chips, flip chip/package assemblies, transistors, capacitors, microprocessors, random access memories, etc. In general, semiconductor devices refer to any electrical device comprising semiconductors.
There exists a need in the semiconductor device art for a device that combines the performance improvements of SOI technology, STI technology, strained silicon technology, and bulk silicon technology. There exists a need in this art to provide a hybrid semiconductor device that comprises SOI regions and bulk silicon regions formed on a common semiconductor substrate comprising a strained silicon layer.
These and other needs are met by embodiments of the present invention, which provide a semiconductor device comprising a semiconductor substrate comprising a base layer and a silicon germanium (SiGe) layer formed on the base layer. A silicon layer is formed on the SiGe layer, wherein the SiGe layer contains a first region in which an isolation region is formed therein, and a second region. A plurality of field effect transistors (FET) are formed on the substrate, including a first FET formed over the isolation region in the first region and a second FET formed in the second region.
The earlier stated needs are also met by certain embodiments of the instant invention, which provide a semiconductor device comprising a semiconductor device comprising a base layer and an SiGe layer formed on the base layer. A silicon layer is formed on the SiGe layer. An insulating region extends through the silicon layer into the SiGe layer and portions of the insulating region extend alongside and under the silicon layer, and a transistor is formed in a portion of the substrate overlying the isolation region.
The earlier stated needs are also met by certain embodiments of the instant invention, which provide a method of manufacturing semiconductor devices, the method comprising providing a semiconductor substrate comprising a SiGe layer formed over a base layer. A silicon layer is formed over the SiGe layer. A first region and a second region are formed, spaced apart from each other, on the substrate, wherein the first region comprises an isolation region. A first FET is formed over the isolation region in the first region, and a second FET is formed in the second region.
This invention addresses the needs for an improved high-speed semiconductor device with improved electrical characteristics.
The foregoing and other features, aspects, and advantages of the present invention will become apparent in the following detailed description of the present invention when taken in conjunction with the accompanying drawings.